As density of circuits, such as multi-core, application-specific integrated circuits (ASICs), continues to increase, many designers are working towards three-dimensional (3-D) stacked chip technology as an emerging trend in the industry. One reason for this work is the decreasing size of transistors, which allows for more components to be placed within the same chip footprint. As this happens, the relative distance between components grows larger. For example, consider two 1 μm transistors connected by 1 mm of wiring. A signal that travels from one device to the other will cross a distance equivalent to 1000 transistor lengths. If, however, the size of the transistors decreases to, for instance, 1 nm, but the separation between components remains the same, then the distance now equates to 1,000,000 transistor lengths between the two components. The signal thus needs to travel several orders of magnitude further in terms of relative component scale. Despite several techniques proposed to shorten wiring length connecting remote parts of a same chip, problems of wiring density and limited number of escape routes continue to exist. This has led to the concept of three-dimensional chip stacking or vertical integration of chips or components. For instance, if a central processing unit (CPU) floating point unit and register file are relatively far apart from each other on a chip or die, it is possible to locate the floating point unit within a separate die, and place this separate die directly over the die containing the register file, and thus replace a long horizontal distance between components with a relatively short vertical distance.
A significant issue remaining with a vertical integration approach is the limited number of wiring escapes, for example, in a three-dimensional stacked configuration. A parallel electrical data bus is usually required to produce enough bandwidth without increasing the data rate of a single line beyond acceptable limits for electromagnetic noise. However, it can be challenging to interconnect multiple three-dimensional layers with a parallel electrical data bus that has properly equalized lines.